The invention relates to a method for the generation of instruction words for driving functional units in a processor, the instruction words comprising a plurality of instruction word parts. Each instruction word part respectively controls a functional unit. A sequence of primary instruction words, which originate from a translation of a program code, undergoes fractionation into program words of a program sequence. During the program sequence, under the control of a program word which has an information part at least of the width of an instruction word part, an instruction word is taken from a row—determined by a reading row number—of an instruction word memory that can be written to row by row and is altered by means of substitution of an instruction word part with the information part of the respective program word. It is then written back to a row of the instruction word memory, the said row being determined by a writing row number. After generation—effected in this way—of an instruction word corresponding to the primary instruction word to be executed, the instruction word is provided to an output for driving the functional units.
The invention furthermore relates to an arrangement for carrying out the above method.
The German Patent Specification DE 198 59 389 C1 describes an arrangement for controlling functional units in a processor. As discussed therein, the program word contains, in addition to an information part, at least also the information about the writing and reading row numbers for the instruction word memory. This necessitates a large width of the program words which, on the one hand, with the requisite processing and decoding of the control information, produce limitations in the processing speed of the task-related data. On the other hand, the high data width of the program word processing necessitates high outlay on hardware in the realization of the processor.
It is an object of the invention to reduce the data width of the program word to be processed in order that the outlay on hardware and thus the costs for the realization of the processor are kept low.